Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. At least 3 years of experience in physical design and methodologies. Experience with place and route tools, commands, debugging, and techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture. Experience with physical IP integration (e.g., memories, IOs, analog PHYs). Experience with silicon interposer design. Experience crafting physical design automation flows. Experience with EMIR parameters, analysis, violation mitigation, and tradeoffs related to power grid design and augmentation. Experience in advanced process nodes with base and metal layer DRC analyses and problem resolution. Role Description: In this role, you will shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will develop custom silicon solutions, contribute to innovative products, and verify complex digital designs, focusing on TPU architecture and integration within AI/ML systems. Position Details: As an ASIC Physical Design Engineer on the Chip Implementation team, you will work on the physical implementation of ASICs in advanced technology nodes. Organization Context: The ML, Systems, & Cloud AI (MSCA) organization at Google designs and manages hardware, software, and infrastructure for Google services and Cloud, emphasizing security, efficiency, and reliability, with a focus on shaping hyperscale computing's future. Salary and Benefits: The US base salary range is $132,000-$189,000 plus bonus, equity, and benefits. Salary is role, level, and location-dependent. More details are available during the hiring process. Benefits information can be found at . Responsibilities: Work on physical design including place and route, EMIR, static timing, and verification. Utilize industry-standard EDA CAD tools for custom design work, optimizing Power, Performance, and Area (PPA). Google is an equal opportunity employer, committed to diversity and inclusion. For accommodations, please complete the form at . #J-18808-Ljbffr Google
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